1. Field of the Invention
The present invention relates to a semiconductor memory device which is capable of reducing a data bus line load to enhance a data transfer speed.
2. Description of the Prior Art
Generally, data bus lines are included for data transfer in semiconductor memory devices such as a dynamic random access memory, a static random access memory, a read only memory and the like. The data bus lines have loads such as a routing capacitance, a fringing capacitance, a sheet resistance and the like, resulting in a delay in the data transfer. The routing capacitance is commonly called an intrinsic capacitance and produced between the data bus lines and a semiconductor substrate. The fringing capacitance is commonly called a coupling capacitance and produced between adjacent ones of the data bus lines.
A conventional 16M (mega) static random access memory (referred to hereinafter as SRAM) will hereinafter be mentioned with reference to FIG. 1.
Referring to FIG. 1, there is shown, in block form, the conventional 16M SRAM. As shown in this drawing, the conventional 16M SRAM comprises 64 memory blocks 1001-1064, each of which has a memory capacity of 256K bits. That is, each of the 64 memory blocks 1001-1064 includes 128 memory cells in the horizontal direction and 2048 memory cells in the vertical direction. Generally, as the semiconductor memory device becomes larger in scale, the bit line loads such as the sheet resistance, the routing capacitance, the fringing capacitance and the coupling capacitance are increased. The increased bit line loads have a bad effect on the data input and output, resulting in a limitation in the number of memory cells in one memory block. For this reason, the semiconductor memory device comprises a plurality of memory blocks. Here, the coupling capacitance signifies a capacitance produced at a contact point between the bit line and the memory cell.
The conventional 16M SRAM further comprises 64 first-stage sense amplifier arrays 1101-1164, each of which senses eight output bits from a corresponding one of the memory blocks 1001-1064. Here, the number of the output bits from each of the memory blocks 1001-1064 is 8 as an example, which may be different according to the type of the semiconductor memory device.
The conventional 16M SRAM further comprises 64 second-stage sense amplifiers 1201-1264 for sensing output bits from the first-stage sense amplifier arrays 1101-1164 in the unit of 8 bits by weight, respectively. Output bits from the second-stage sense amplifiers 1201-1264 are placed on eight data bus lines in the unit of 8 bits by weight. The conventional 16M SRAM further comprises eight third-stage sense amplifiers 1301-1308 for sensing bits on the corresponding data bus lines, respectively. The data bus lines have such long lengths as to input the cell data from all the memory blocks 1001-1064.
As a result, as the semiconductor memory device becomes larger in scale, the data bus line is increased in length, resulting in an increase in the load. The increased load of the data bus line causes a delay in the data transfer.
Further, in order to drive the data bus line with the increased load, the sense amplifier must be increased in size. The increased size of the sense amplifier reduces a data sensing speed thereof and increases a lay-out area thereof.
In this connection, a data bus line load reduction circuit is required to reduce the data bus line load, so as to increase the data transfer speed and reduce the lay-out area of the sense amplifier.